Hello All,
I have PCB Design were I have 125 vias when I zoomed the design then at that point I have 15 vias.So when I run the script I should get 15 vias only not 125 which reduces the time.How can this be achieved through script.Kindly help me.
Thanks & Regards,
Kannan
Hello, I recently re-installed Design Capture and now I cannot create an overbar for a net name using the tilde character. Any ideas how I can solve this problem? Is it a font issue?
Thanks,
joe
Hi,
how to make effectively a memory array? I have built a cell (schematic and layout). For small array, the placement can be done by manually. How to built bigger array and keep higher density? I know, the placement can be done by scripts, but I am not familiar with the AMPLE language.
Thanks a lot!
Best regards,
Lukas
Hello all,
can you please help me to choose the graphics card to my new notebook... not to have a problems with performance, driver..... (or minimum)(best supported)?
1) I can choose the NTB with integrated graphics card on chip (HD4600.....on Intel Core i7-4810MQ) AND AMD FirePro M6100M w/2GB GDDR5
or
2) either integrated HD4600 OR.... AMD Radeon HD 8790M 2G GDDR5
or
3) without integrated graphics card .... NVIDIA Quadro K1100M w/2GB GDDR5 or NVIDIA Quadro K2100M w/2GB GDDR5 or AMD FirePro M5100 w/2GB GDDR5
I would prefer NTB with the option 1 but I'd like to know some experience , known issues, troubles... to better decide.
Can somebody recommend me the the best solution?
Many thanks
Martin
- Does vesys harness support measuring from a single reference node? See the highlighted measurements shown below (FIGURE-1),
- Can the insulation tube in vesys be denoted the same as shown in (FIGURE-1), i.e. can we have the insulation with a fill pattern?
FIGURE-1
- Connector table (FIGURE-2) shown below, is it possible to customize the table, i.e. change the column title and have customer specific data in one of the columns?
FIGURE-2
--- - Terminals don’t show up in the BOM report, see the attached, how do we get the terminals listed in the BOM - (Lumen-HILUX-BOM.pdf)
I need to add some vias in the design. I have a integrated project that I have done and I need to add a couple of vias for routing and pouring now.
The add via button is greyed out. How do we add the additional vias? In a old "normal" design we have full control. Is it dictated on the front end in xDX ?
Thanks,
Lyle
Hi
Is my formula correct for that what I want to do? see picture.
I work with Mentor PCB Expedition 2005.3 and CES Version 5.0
Max. lenght for all signals 177.8mm
Length matching between strobe signals 'IDE_IOR@' and 'IDE_IOW@' and data signals 'IDE_D[0-15]' Max. 11.4mm
Length matching between data signals 'IDE_D[0-15]' Max. 5.08mm
Length matching between strobe signals 'IDE_IOR@' and 'IDE_IOW@' Max. 2.54mm
Is there an other way to create the correct formula?
Thanks
Best regards
Moreno
What are people's first impressions about the new communities?
Hello,
We have been working with NVIDIA on the performance issues related to their latest drivers. At this time we validated that the driver released this week, 320.92, does have performance improvements specific to Expedition PCB. Our results show if you use this latest driver with the Workstation App - Dynamic Streaming Global Preset, the performance is comparable with the 276.28 version of the driver. If you compare the 276.28 Base preset to the 320.92 Workstation preset the graphics system is actually ~30% faster based on the initial evaluation we have done.
We continue to evaluate this driver with our suite of NVIDIA graphics hardware but at this time it appears anyone who was seeing performance issues with the latest driver should load this one and evaluate. Please make sure you use the Workstation App - Dynamic Streaming Global Preset since it will not be remember when you load a newer driver.
It would also be helpful if you find success or issues with this driver, please respond to this thread.
Regards,
Jerry Suiter
Product Marketing Director
Expedition
Hi,
How to add unique sheet name on a repeated block in dxdesigner?
Version: EE7.9.5
Thanks.
Hi,
I have to create a BGA footprint with irregular pad locations. I have the X & Y co-ordinates with me. Could some one provide a suggestion how to create a BGA footprint in PADS tool with X & Y co-ordinates in txt file?
how to connection on the connector has multiple solder pins with same pin number, it is NOT required to have multiple pins on the schematic?
Greetings,
I'm a new user of FloEFD and I'm running into trouble with one of my simulations.
Description of the Simulation:
I am Simulating a Simple box with 2 Outlets and 3 Inlets and using air as my fluid. The Inlets have different temperatures assigned to them and I am interested in the temperature on the outlets.
Problem:
When I run the simulation an error occurs "Vortex crosses the pressure Opening" which make my values at the inlet in accurate due to contamination.
Question:
How do I specify pressure as an Outlet instead of an Opening? is this possible with FloEFD?
Any Suggestion would be most welcome.
Thank you.
Gary,
To use PartQuest now you must link to a Digi-Key account. I have tried two different browsers and can't get this accomplished.
John W.
Hi Everyone
I just started with scripting so I don’t have a lot of experience with scripting. Last Friday I have been trying to find a way to close the 3D View screen via Automation.
Does anyone know if this is possible and if possible how it has to be done? I found a way to open the 3D View with the Add PCB View button in the Window Menu, unfortunately there is no close button in that Menu, so to close the 3D View I need something else. The only way I know to close the 3D View is with the x in the upper right corner, anyone know how I can access this?
What I can for example is “pcbDocObj.close” but this will close the complete Layout, but I just like to close the 3D View with the Automation.
So if anyone has a idea or can give me a hint how I can do this, that would be great.
Thx alot in advance
BR Ralf
One of the Aberdeen reports said that (I'm paraphrasing here) "One of the core requirements to having a robust E-CAD system is having a good PCB library". The Mentor library tools make this difficult. Here are some examples:
All these different tools make it much more difficult for librarians to create library parts. In our environment we add on average 300 parts a month to our library. Our librarians need one robust tool to create library parts, both in the netlist flow and the Expedition flow. In my opinion, because Mentor has no one group in SDD responsible for librarian tools, all we have now is a bunch of point tools that address certain types of parts. Mentor needs to get organized, quit the infighting between the different factions and quickly come up with a strategy to address this issue.
Do any other companies have this problem?
Thanks for listening,
Tony
Since Mentor has chosen to ignore this area for the netlist flow, we're looking to see if there are any 3rd party schematic symbol editors out there.
Some key requirements:
Able to mine PDF component specifications to get the Pin/Pin number data.
Able to create fractured parts.
Able to check and make sure all pins are accounted for.
Able to check for duplicate pins.
Thanks,
Tony
Anyone already write any code to export CCZ files in 2007.3 or later?
Hi,
When I am compiling a project on Grid which has lot of memory, vsim is creating lot of threads hence the compilation is failing.
Can some one please help how to start Questasim (vsim) which can run only on single thread (or disable threads option)
This project is being compiled in coordination with other tool Calypto catapult.
Compiling C++ file: ../../tb_dct_stream.cpp
# /applics/mentor/questaprime_10_1d/questa_sim/bin/sccom -g -x c++ -Wall -Wno-unknown-pragmas -DCCS_DUT_RTL -DCCS_DUT_VHDL -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=dct -DCCS_MISMATCHED_OUTPUTS_ONLY -DDEADLOCK_DETECTION -I./scverify -I. -I../.. -I./scverify -I. -I../.. -I/applics/mentor/questaprime_10_1d/questa_sim/bin/../include/systemc -I/applics/calypto/catapult_8_0/Mgc_home/shared/include -I/applics/calypto/catapult_8_0/Mgc_home/pkgs/hls_pkgs/src -I/applics/calypto/catapult_8_0/Mgc_home/pkgs/siflibs -I/applics/calypto/catapult_8_0/Mgc_home/pkgs/hls_pkgs/mgc_comps_src -DUSE_STD_STRING -DSC_INCLUDE_MTI_AC -c ../../tb_dct_stream.cpp
#
# QuestaSim-64 sccom 10.1d compiler 2012.11 Nov 1 2012
# ** Error: (sccom-6188) Error creating thread using pthread_create(): 'sccom_thread: EAGAIN pthread_create'. Please use sccom -nothreads.
#
#
# x86_64-unknown-linux-gnu
# make: *** [scverify/concat_sim_rtl_vhdl_msim/tb_dct_stream.cpp.cxxts] Error 11
I've recently switched to a new laptop and re-installed PADS Layout, Logic, etc version 9.2. I had 9.2 on my old laptop (both are Win7) and when I tried to open a file previously created and run on my old laptop, my new laptop gives me an error stating "Job not compatible with current version of program." I have my hardware license key installed, but I can't even open or view the files now.
Any help/recommendations greatly appreciated.
Thank you.