Modul: "XPedition xPCB Layout"
1) Is there a way to find out per Automation, if the "Message Window" is enabled (visible) or closed?
2) When Yes, Is there a way to show/hide this Message Window? (not toggle - exactly: show or not show! /as I want)
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XPedition, Message Window, check if open, open if closed, per Automation...
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ECO to PCB warning: Invalid last Pin detected in Signal
Hi
I'm getting a following warning message when I'm sending ECO from Logic to Layout in a particular design.
Logic and Layput version: VX.0
Line 48 , Section *END*
*END*
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$2
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$3
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$1
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$4
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$5
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$6
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$7
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$8
* *WARNING. ECO Import internal error: Invalid last Pin detected in Signal $$$9
These nets seem to be some kind of "zombie nets" in Layout, they are not connected anywhere but still I'm unable to delete them.
Since PADS Layout seems to f-up the binary files more than occasionally, I've tried exporting the layout as .asc and then importing it back but that didn't work this time.
Is there any way I can fix this to clear these warnings?
Thanks for any advice!
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Question about turning ON and OFF layer visibility in PADS Layout
In OrCad Layout I remember I could turn off all layers by hitting Backspace, then pressing "1" would bring ONLY the top layer. I loved the fact that after hitting Backspace, I could bring ONLY the layers that I was interested with just a single keystroke per layer. Can I mirror this 1-keystroke-per-layer functionality in PADS Layout?
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is it possible to take layout in print screen view ??
Hi, i need to export the layout in screen view mode is it possible to take in PADS 9.5 ??. i tried in created PDF method.but i could not able to do.Please help any one to take the screen view type of printing ???
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Report Writer problem on VX1
When I work with Xpedition VX1 64bit if I press the Report Writer button to generate the necessary files, the program generates the folder ./vbreport/output that contains no files .mdc.
Xpedition creates an empty folder.
Instead there are files in ./vbreport/work.
I have installed the patch X-ENTP_VX.1_update3_ESDM.ix64, butthe problem has not been resolved.
What can I do?
Thanks, Franco.
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Comparison of Mentor tools versus Tanner EDA
I'm looking for any feedback on how DRC, LVS, Schematic, Layout and SDL tools compare between Mentor and Tanner EDA.
I've just started a 30 day evaluation of Tanner EDA tools on my Windows laptop and am going through the tutorials.
I think the target use for Tanner tools is lower-end, mixed-signal IC designs and some MEMs.
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How to get SolderPaste area from within padstacks in component placed in layout?
Tried to get pointarray with the object "FabricationLayerGfxs(epcbFabSolderpaste, epcbSelectAll, epcbSideTop,True)"
It reads any Solderpaste drawing objects in layout that is drawn during design, ok. But It does not read the Solderpastes in the Components(which mean placed as Padstacks).
What should I add into below?
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Dim mskeng
Set mskeng = CreateObject("MGCPCBEngines.MaskEngine")
Scripting.AddTypeLibrary ("MGCPCBEngines.MaskEngine")
Scripting.AddTypeLibrary ("MGCPCB.ExpeditionPCBApplication")
Dim stenColl
Set stenColl = pcbDoc.FabricationLayerGfxs(epcbFabSolderpaste, epcbSelectAll, epcbSideTop,True)
Dim stenUs, shapesCu
Set stenUs = mskeng.Masks.Add
Set shapesCu = stenUs.shapes
Dim stenobj, pnts
For Each stenobj In stenColl
pnts = stenobj.Geometry.PointsArray
Call shapesCu.AddByPointsArray (1 + UBound(pnts, 2), pnts)
Next
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Using favorite my_parts in xDxD
Hello folks,
I have expected the favorite my-parts to behave exactly the same as if I put a component from DxDB. I have noticed that this is not the case. Following a description of the differences and a question.
Is this another case of Works As Designed, where designed is not exactly what the user expects it to be?
I open xDxD and imagine I choose a component from DxDB, and drag it in the favorite section.
Now let see the four different way of put it on the schematic.
1 dragging from the DxDB window directly into the schematic.
The component will be placed and has all its pins and property defined as has been all along.
2 dragging from favorite unassigned
(as default the favorite components will be slot unassigned)
and onto schematic
all seems ok, apart from the pins that are unassigned
3 dragging from favorite slot 12
we change to slot and all seems ok
and drag it to the schematic
Perfect, all as expected.
Now for completedness just the same unassigned from DxDB
4 dragging form DxDB unassinged slot
Everything in parameters. As I am happy as it is I close the project, close xDxD and go sleep...
The next day I reopen xDxD and the project and want to use the favorite part.
2b dragging from favorites unassigned
before I even grab the favorite component I notice that the values of the favorite components are lost.
and if I place something like this on the schematic it has half of the information it had before.
Also the visibility of some property has changed.
3b dragging from favorite slot
changing the slot information does only influence the slot but not the missing properties.
3b dragging from DxDB
Placing the same component from DxDB still works as expected
Does this mean that favorite component are stored only partially and upon reentry in the tool they will be not my favorite parts anymore, but merely the part that was dragged from DxDB without any property, as selected with DxDB?
If this is so, what is the purpose of the favorite parts?
Thanks for any clarification.
Matija
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Set default fan-out for SOIC/QUAD and BGA in PADS ROUTER
Hi All,
I have to create a component with SOP family but when doing the fan-out in PADS ROUTER, the Component Properties always set default fan-out for BGA family. SOIC/QUAD is what Iwant to be. Can anyone help for me?
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Problem with importing pins from CSV file.
Hi there,
I am having trouble getting the "File -> Import Pins" operation to work in the DxDesigner 9.3.1 Symbol Editor.
I have created a CSV file, attached, but when I do the "File -> Import Pins" operation I don't see the pins in the Pins Window.
I also get this error message in the console
"line 1: column Pin Order not found"
Any idea what I am doing wrong?
Thanks
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Excel Export In CES
Hi Experts,
Any way to export data from CES as .xls?
We may export it as .csv but its encrypted so I couldn't see whats in it. (or) Do we have any option to decrypt ecsv?
My wish is to export CES to excel and to review some Constraint classes and Net classes in a Excel against my design input.
- Arunraj
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Stretchable interconnects
Anybody had any success of carrying out horseshoe shaped interconnects (not by exporting from AutoCad or any other CAD)? Maybe using macros or some special meandering options?
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HCELL selection for LVS
HCELL selection can be a controversial topic. I would like to describe a few different techniques, the rationale behind those techniques, and hopefully generate some discussion based on your experiences.
One technique focuses on performance. In the interest of fastest turnaround time, we can choose cells based strictly on the potential time savings that choosing any particular cell may bring. Any cell containing just a few devices, and then placed just a few times, would offer little value from the standpoint of performance. On the other hand, a cell that contains several thousand devices, and placed multiple times, is a good candidate for the hcell list. Calibre Interactive can help create an hcell list of this nature. From the command line, it can be invoked with "calibre -gui -lvs". Several fields will need to be filled in for netlist names, top cell names etc. The process is described in the "Calibre Interactive User's Manual" in the section titled "Performing Hcell Analysis in LVS". A high performance hcell list may have a surprisingly small number of hcells... Possibly less than 10 or 20 cell names. While the performance aspect of this method seems clear enough, I do sometimes wonder if the small number of hcells ever has a negative side effect of increased difficulty for LVS debug.
Another technique focuses on "design methodology" instead of performance. Some people use hcells as a means of enforcing a design methodology where hundreds or thousands of cells with the same name in the layout and source are expected to match at the cell level. The "-automatch" switch, or an exhaustive hcell list of practically all the layout and source cells may be used for this method. It's not necessarily best for performance, and can lead to nuisance errors in many cases, but many people use this method. I would be interested to hear your opinions related to this method.
A third technique begins with listing all the standard cells, and adding certain other cells based on some criteria. I presume that familiarity with the design is necessary for this method. I haven't used this method myself so I'm a little vague on the details. If you have had good or bad experiences with this third method, please share.
I have often wondered if Calibre could offer a simple and automatic hcell selection option that gives optimum performance, avoids false errors and promotes easy debug. Maybe our collective discussions will lead to the answer.
I will collect and summarize replies for this thread into a document we can refer to. Here's a link to that document: HCELL selection methods
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Add via option in padstack editor is grayed out
I need to add some vias in the design. I have a integrated project that I have done and I need to add a couple of vias for routing and pouring now.
The add via button is greyed out. How do we add the additional vias? In a old "normal" design we have full control. Is it dictated on the front end in xDX ?
Thanks,
Lyle
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DDR 3 Layout across 2 pcbs
I have a design with an FPGA and DDR3. The DDR3 is on a daughter board of the FPGA board. I'm starting layout of the DDR3 board. I have to length match the total length of the Address and Data lines from the FPGA to the DDR3 (across 2 boards). It looks like I'll have to set up length rules for each board, then export each trace's length to a spreadsheet and match them by hand. Does anybody know of a better way? My PADS Router package does not include autorouting with length rules.
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DxD Change PDF connection dot size
Is there a way to change the size of the connection dot when Export -> PDF is used? Ideally a setting in dxpdf.ini that could be saved in the corporate WDIR.
It appears very small on our schematics. It practically disappears if the schematic is printed (and certainly if it is then photocopied), it is also problematic when a projector is use, or tools like webex.
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Multiple via under pads
I am trying to place an array of vias under some pads (thermalpads, for example) but I do not manage to place them.
I enable the vias under pads in the "editor control - pad entry" and with F2 key (Fan out) I manage to place one via in the center of the pad but sometimes one via is not enough.
I have read the documentation and tried to generate a configuration file but it is not working.
Is there a tutorial or an example that I can check in order to place the multiple vias under pads? Can I do it somehow without configuration file chosing the number of vias to be placed and their distribution (4x4, 4x2, 6x1, ...)?
Thanks in advance.
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Regarding Decal Symbol Creation
I have designed a certain RF component which is in the form of Copper Traces Artwork. I need to create this artwork at decal level so I can bring it in the layout every time I use it in my schematic. I have done a similar thing at Decal level but it was only required top layer for the artwork I created. This time I need not only to access the top layer but also inner layer 2 to complete this new artwork. My final board stack up is a 4 layer board. I generate this new artwork at Decal level by setting the layer definitions to 4 layers and complete my artwork on 1st and 2nd layer, however every time I leave my library and come back to it, after saving my artwork of course, I only see the layers top and bottom and there is no inner layers (L2 and L3), any idea of why is that?
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xDx VX1 - packager
Hello all,
I'd like to share my experience with packager.
I did a schematics with a connector (68 pins).
I placed individual pins of this connector on sheet (50 and 60) manually.
I didn't put a REF. DESIGNATOR to pin 50 of the connector - I forgot.
I was very surprised with the result ..... after packaging my design.
After this I realized that:
1) If I don't place manually the ref. designator to the pin symbol the packager change the pin number !
2) If I place the ref. designator the packager doesn't change the pin number. (this I'd expect)
I would expect the packager doesn't change (doesn't touche) my pin number in any case!! The opposite is the true.
Is it right behaviour?
Thanks
Martin
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Library Builder program?
Have Mentor Graphics got available a Library Builder type program.
I have seen the demos of the OrCAD library builder where you can generate footprints from pdf data and more and it looks very good.
Have Mentor got an equivalent program to this available.
Also check out the OrCAD youtube channel which shows videos of how there tool works.
http://www.orcad.com/sites/orcad/files/resources/files/OrCAD_Library_Builder_DS.pdff
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