I have a script that opens an Expedition PCB design, does something with it, and then closes the tool.  The problem is that when an Expedition PCB is undocked (and not docked yet) the script fails and this leaves the Expedition tool running (with the design open) - not good.  Here are my questions:

• Is there a function that can be used to find out if the Expedition PCB is undocked?  If so, what is it?
• If there isn't a function is there any other way to find out if the PCB is in an undocked state?
• If there isn't a way to find out if an Expedition PCB is undocked or not then how can I close the Dock window that pops up upon open the PCB in Expedition?  I know of a method but it's not robust.

I am using EE795.  Thanks for help!

Varun

As design get larger and larger, we found Valor NPI run time begins to be an issue. On some of Allegro databases, it takes 8 hours ~12 hours for fab and assembly checks. Here is a typical break down of total running time for those databases:

Power and Ground Checks taken 60~90% times

Netlist validation taken 10-30% times

other total taken only 10%

I have been morniting Valor NPI process and found it  need hours to do following process due to very tiny slivers in database

Power Pads Processing

Enlarging Plane shapes

Generating Shapes Netlist

However, you can't always avoid tiny slivers in your layout. How you can descrease the process time?

Yanfeng

I found a discussion on this topic but the links were broken.

Hyperlynx (Newbie question)

The response to the question looked interesting:

"the R-L-C Circuit is a good starting with HyperLynx Analog (HLA) -> http://supportnet.mentor.com/reference/tutorials/10390.cfm . I think you have watched this one already. It is showing the principals of analog simulation to an absolute beginner, but for more complex systems with ICs and subcircuits you need a deeper knowledge about DxDesigner and Spice language itself. I have already been searching through supportnet, my favourite resource for background information about Mentor products, but I could not find a relevant example or tutorial."

Is there a link that works to the following recommended totorial

http://supportnet.mentor.com/reference/tutorials/10390.cfm

I get the following error when I click the link:

Not Found

We're sorry, the page or resource you requested either does not exist or is not currently available right now. Please check the URL for proper spelling and capitalization, or use the site search box to search Mentor SupportNet. If you are unable to find the information you were seeking, please feel free to open a Service Requestor contact your local support office.

Thanks

Mike

I accidentally set my calendar forward a month, and I used Pads Logic and Layout while the date was set forward.  I went home for the night and windows must have done an update overnight and reset the clock to the correct date.  When I returned in the morning and tried to open Pads layout, I got this error

LICENSING FAILURE!

Licensing error:

     The system date/time appears to have been set back.  Cannot continue.

     Please correct the system date/time and restart the application.

I then click OK and get this error.

PADS Layout

Security system wasn't properly initialized: License request for pwrshell feature failed.  The program will run in Demo mode.

Pads will then open in Demo mode.  If I reset system clock to be a month ahead again then everything works fine.  However windows updates the time every 15 minutes which causes PADS to crash, and I lose all my work.

I assume this is a security feature that prevents people from setting their system clocks back a few months or years and getting extra time with their license.  I have 9 years left on my license so that is not the case here.

How can I get PADS to synch up with the real clock, so it will use the actual date instead of a month in the future?

I am using PADS 2007.4 running on windows XP.

Thank you,

Mentor,

As we are pushing towards deploying our DXD release there has been a repeating question from executive levels on the termination of the Design Capture product itself.

What are the long term support plans for Design Capture and is there a period where it will be terminated?  (3yrs - Xyrs from now)

I understand that Mentor will not pro-actively terminate a product before migrating the user base etc, but is there any projected roadmap/ initiatives in place or hypothetical for the decommission of Design Capture?

From my perspective it will continue as you have enough customers supporting the sustaining needs for the tool set, but you are no longer investing in DC development & feature improvements etc.

My issue is trying to clarify a mentor response and stance on DC as we push past into DXD workflows

Thanks & please respond if possible or forward to the right contacts.

Chris Smith

Application Support Analyst | PCB Services

National Instruments |www.ni.com

chris.smith@ni.com

Hello, I am trying to create a new dxdesigner schematic by backwards annotating a layout in PADS. I was able to link to the two projects, but when I try to backwards annotate I get a lot of error messages like this:

pcb: Error 6112: file Schematic1.eco, line 44: Couldn't create new C_0402 package C102

Does anyone out there know how to fix this, or a better way to go about this in general?

Thanks,

Nathan

Hello,

I am having a difficult time trying to track down these errors I get with the packager. There are many similar:

ERROR: There is no Part Number: IAN0-0004 in the Parts
DataBase for symbols with Part Name: LM339 and Part Label: LM339.
[Please add the Part Number to the PDB either directly
or by having the project file point to a PDB that contains it.]

The project uses the central library, and the parts are definitely in the central library, because when I make a change, the DxDesigner asks to upgrade the symbols. I am at wit's end trying to diagnose this problem.

Thanks,

Hi all,

   New to Pads VX. I am looking for a way to set the setup files (default) for Pads layout so multiple users are accessing the same file.

I have found the default.asc and *.stp files located in the SDD_Home\Settings folder. Is there any way to change where Pads looks for these files?

Possibly placing the files on a shared network location and having Pads use that location. This would insure all users are starting with the same files.

Is there another way to set this up so all uses can access the same file?

                                             Thanks

Does anyone have a good idea of when PADS Flow VX.1 will be released?  Trying to decide if I should have the IT group install VX.0 in over 20 users computers or wait a few weeks for VX.1.  The BSD Release Information by Product (September 2014) showed VX.1 for Pads November 2014.  http://supportnet.mentor.com/news/bsd_planned_releases.cfm

It seems body to body clearance violation errors occur whenever a part outline touches another part outline.  This would seem to jive with the intent of the rule, but it doesn't.

The problem is that part outlines with a thickness violate the rule whenever any part of that thick outline touches another outline.  This is a problem.  To look at it from another perspective... When I create a part, I create it based on spacing/dimensions provided in the manufacturer specifications for the part.  So, if the manufacturer suggests a courtyard of 100mil x 100mil, I draw an outline of 100mil x 100mil.  As long as another part does not violate my 100mil box, I'm good.  But if I give that outline a thickness of, say, 10 mil, then any parts placed on 100 mil centers will violate.  This is not because the courtyard dimensions have been broken.  Its because the courtyard line thicknesseshave been broken.

This is a flaw.  No one designs part decals according to manufacturers recommendations... oh, and by the way, be sure to remember to take into account line thicknesses in PADS.  Every outline would now require a calculation to adjust for the thickness, which, in addition to the additional work to create each new part, also makes decal creation more prone to to calculation errors.

There is no doubt that this is a defect, I'm just wondering if this was designed into the tool on purpose, or just an oversight.

(Before anyone proposes this as a solution, I'll go ahead and nip it in the bud... Changing the line thickness of the library part is not a solution to this problem.   It's a work around, which does not truly resolve the issue...  Line thicknesses may play other important roles in a design, which, in my case, they do.)

Dear community,

This is Hai from Lorentz Solution.

I have a question regarding installation of the ODB++_Inside_Cadence_Allegro_9.4 in Linux.

Since we want to export ODB++ format file from Cadence Allegro, I downloaded the Redhat version of ODB++_inside installation package (free of charge) from the official website (http://www.odb-sa.com/resources/odb-inside-for-cadence-allegro)

I unzipped the package and it generated a .aol file:

ODB++_Inside_Cadence_Allegro_9.4_Setup.aol

I read some installation guides for mentor software, and all of them mentioned using Mentor Install Program (MIP) to install mentor products. However, I didn't find a place to download it.

In windows OS, ODB++_Inside_Cadence_Allegro_9.4_Setup.aol can be extracted, and in the extracted folder, there is a mgc_install file which can be run in Linux. However, near the end of installation when it tried to perform some post installation script, there is an error message pop up saying syntax error. Then we checked this post installation script, looks like it is in windows language. I believe that is reason of syntax error showing in Linux.

I am wondering is there any hint on the installation? or should we use the latest MIP, where to download it?

Thank you for your help!

Hai

Using Dx/Expedition 7.9.1 workflow.

When I run Report Writer to extract central library data it crashes with an error

Looking at the dbcreate.txt file the error reported is

ERROR :  5 - Invalid procedure call or argument

When a colleague runs report writer on the same library it completes correctly.

This leads me to believe that there is some form of corruption in the install of Report Writer on my pc.

Any ideas as to why I get this error and more important how to fix?

Hi,

I'm currently trying to setup extraction for the IBM, soi12 PDK (Calibre V2014.2 I think) .  Unfortunately, I'm having a few issues. 

For one, when I select "Use Names from Layout"  in the PEX setup form, no PEX netlist is generated until I first run LVS in the PEX run directory. There are no errors or warnings printed to the transcript.  Secondly, even if I run LVS first and successfully generate the PEX netlist, I'm not able to use the map schematic net tool for nets not connected to pins (as I seem to be able to if I select "Use Names from Schematic".   

I realize that I'm probably missing something fundamental, but I've not been able to understand this behavior from the documentation.  Any help would be greatly appreciated.

Regards,

Justin

Morning people,

I have 1 project (and would like to keep it to one project if possible), with 20 circuit diagrams in. I would like to know the best way to lock 5 of these drawing down to only a certain group of people, and then the next 5 to the next group of people. I've been using domains but not entirely sure this is best practise.

so i would have:

group1 would have Restricted 1 and General domains in their profile

and group 2 would have Restricted 2 and General domains in their profile.

But the restricted drawings is set to rise to about 45 I was wondering if there is a better way to do this than creating (potentially) 46 different domains.

Any suggestions much apreciated

Regards

Andy Middleton.

HCELL selection can be a controversial topic. I would like to describe a few different techniques, the rationale behind those techniques, and hopefully generate some discussion based on your experiences.

One technique focuses on performance. In the interest of fastest turnaround time, we can choose cells based strictly on the potential time savings that choosing any particular cell may bring. Any cell containing just a few devices, and then placed just a few times, would offer little value from the standpoint of performance. On the other hand, a cell that contains several thousand devices, and placed multiple times, is a good candidate for the hcell list. Calibre Interactive can help create an hcell list of this nature. From the command line, it can be invoked with "calibre -gui -lvs". Several fields will need to be filled in for netlist names, top cell names etc. The process is described in the "Calibre Interactive User's Manual" in the section titled "Performing Hcell Analysis in LVS". A high performance hcell list may have a surprisingly small number of hcells... Possibly less than 10 or 20 cell names. While the performance aspect of this method seems clear enough, I do sometimes wonder if the small number of hcells ever has a negative side effect of increased difficulty for LVS debug.

Another technique focuses on "design methodology" instead of performance. Some people use hcells as a means of enforcing a design methodology where hundreds or thousands of cells with the same name in the layout and source are expected to match at the cell level. The "-automatch" switch, or an exhaustive hcell list of practically all the layout and source cells may be used for this method. It's not necessarily best for performance, and can lead to nuisance errors in many cases, but many people use this method. I would be interested to hear your opinions related to this method.

A third technique begins with listing all the standard cells, and adding certain other cells based on some criteria. I presume that familiarity with the design is necessary for this method. I haven't used this method myself so I'm a little vague on the details. If you have had good or bad experiences with this third method, please share.

I have often wondered if Calibre could offer a simple and automatic hcell selection option that gives optimum performance, avoids false errors and promotes easy debug. Maybe our collective discussions will lead to the answer.

I will collect and summarize replies for this thread into a document we can refer to. Here's a link to that document: HCELL selection methods

Hi guys, i just installed fedora 20 and Quartus II 13.1 with Model Sim Starter Edition.

I downloaded all required packages, but when i try to run modelsim, it shows me this msg:

[root@localhost Downloads]# vsim

Error in startup script:

Initialization problem, exiting.

Initialization problem, exiting.

Initialization problem, exiting.

    while executing

"EnvHistory::Reset"

    (procedure "PropertiesInit" line 3)

    invoked from within

"PropertiesInit"

    invoked from within

"ncFyP12 -+"

    (file "/home/rodrigo/altera/13.1/modelsim_ase/linux/../tcl/vsim/vsim" line 1)

** Fatal: Read failure in vlm process (0,0)

I tried to reinstall and sam thing happened. I tried downloaded Quartus 13.0 and same thing occurs.

I read in a ArchLinux forum that maybe it is a problem with an update on freetype package, but i just dont know how to fix it.

Somebody knows what this is?

Using DxD/Expedition 7.9.1 workflow with DMS 7.9.1.5

What I would like to do is export part number, cell reference and padstack information from out of DMS so that I can include it into an excel spreadsheet.

I can see that the information is in DMS in the library/Mapping section and I can view the individual settings for each part.

However what I would like to do is export this information for all parts (in a single transaction) and then be able to produce a report of part number to cell reference to padstack reference (and maybe even pad reference).

has anyone got any ideas how this can be achieved or even if there is a better way to obtain this info than from DMS?

Attached is a picture showing a typical part within DMS and I have highlighted the fields that I would like to export into my spreadsheet.

Team,

Todays meeting was a fruitful one and I believe we agreed to the following:

1. The 15 minute presentation would consist of no more than 5 slides.

2. The first slide would be a re-statement of the problem areas within the customer, as identified through other community threads.

3. We may or may not include a swimlane if we feel it would be prudent to highlight the pilot process. Initial feelings are that this would not be necessary.

4. We need to agree on a direction for the pilot, knowing we have 3 months, we need to compile a list of objectives, and document a flow.

5. Initial thoughts were to focus on change and configuration management. Other areas we may consider include, systems (functional design), manufacturing, service.

I propose to add the slides here as we agree on the content.

As for the Pilot, I have a few questions/suggestions for the group as we push forward.

1. Are we proposing a green field pilot, or will we want to migrate some of their existing designs?

2. Do we want to consider first pass generative?

3. Will our current implementation of effectivity be simple enough, yet complete enough, to answer the configuration problem?

4. How much integration to the rest of the enterprise do we add in? Teamcenter? MCAD? etc...

5. API/Extensibility exposure. I am sure there will be some reporting requirements, but what else may we want to consider? Bridges? Web Services?

6. The Publisher piece is essentially free, I think we should include this in the pilot.

I am not saying we have to document any of this, but we should at least have these concepts in mind whilst building a proposal.

I am also sure that there are 101 other things we could add to this list, but right now I am thinking outside of the core tools.

Hello,

When I try to write a VB.NET applikation for usage of DxDesigner (EE7.9.5) I get following error message inside VB.NET.

With VBScript this line does not make any problems.

What am I doing wrong?

Thanks alot

Wolfgang

It seems body to body clearance violation errors occur whenever a part outline touches another part outline.  This would seem to jive with the intent of the rule, but it doesn't.

The problem is that part outlines with a thickness violate the rule whenever any part of that thick outline touches another outline.  This is a problem.  To look at it from another perspective... When I create a part, I create it based on spacing/dimensions provided in the manufacturer specifications for the part.  So, if the manufacturer suggests a courtyard of 100mil x 100mil, I draw an outline of 100mil x 100mil.  As long as another part does not violate my 100mil box, I'm good.  But if I give that outline a thickness of, say, 10 mil, then any parts placed on 100 mil centers will violate.  This is not because the courtyard dimensions have been broken.  Its because the courtyard line thicknesseshave been broken.

This is a flaw.  No one designs part decals according to manufacturers recommendations... oh, and by the way, be sure to remember to take into account line thicknesses in PADS.  Every outline would now require a calculation to adjust for the thickness, which, in addition to the additional work to create each new part, also makes decal creation more prone to to calculation errors.

There is no doubt that this is a defect, I'm just wondering if this was designed into the tool on purpose, or just an oversight.

(Before anyone proposes this as a solution, I'll go ahead and nip it in the bud... Changing the line thickness of the library part is not a solution to this problem.   It's a work around, which does not truly resolve the issue...  Line thicknesses may play other important roles in a design, which, in my case, they do.)