I have a design where the blocks to represent one large fpga have been built inside the design as local symbols. I am now ready to build the Part and associate the block symbols into one cell. Question is, can I build that Part within the design using the local symbols and keep it specific to the design, or do I have to export those symbols into the Central Library and build that Part outside of the design?
Thanks,
Ron
Hi.
I have a schematic with a ground symbol ('device') connected to a 'splice' and wiring from the splice. This looks great on the schematic but gives a problem with Harness:
Problem is I have set up the Ring Terminal dummy connector with ring terminals added to it. Yet I now can not add this Ring Terminal 'connector' to the 'device' or 'splice' in Schematic.
I have raised it as an issue in 'Ideas' but need to know if anyone has a 'work around'. (Remembering of course that I can not add it directly to the harness, as per Classic, because the 'Synchronize' process will remove it.)
Any help would be appreciated.
Hello,
I use Expedition 7.9.4 on Windows 7 but my customer only have a laptop on Windows 8.1. Do you if he can run the PCB Viewer? It do install. But noting append on launch... :-(
Any help?
I would like to open a discussion regarding transitioning from DC to Dx Designer for schematic capture:
At National Instruments we have been using Design Capture since the days of when it used to be Aceplus/Cadnetix; so needless to say we have an extensive
Library and engineering product folders with the following:
15,926 individual schematic symbols
3,452 cell footprints
12,141 PDBs (Parts Databases)
I have heard a mix of user opinions in the past such as "wait as long as you can- until you have to move" or wait a few more revision cycles because of the quantity of code changes/enhancements. We are willing to move forward to Dx if the translators are stable, quality of data is clean without need for workarounds etc.
I personally have concerns about the "ease of translation" if they are using EDIF to migrate schematics. I have seen allot of other tools turn some features into garbage with the 2.0 formats.
I understand Mentor will continue to support DC as long as the customer base is paying support but we don't want to be in a situation where there is an abrupt change in policy or stay on a capture tool that is "dormant" if all of the development is focused towards Dx.
If you have experienced the growing pains & Gains what are some of your observations?
Q. What pitfalls did you discover in your attempt/success in migration?
ex. requirements in reviewing all symbols (did you find problems with mirror views etc), issues with buss rippers going from DC>EDIF>Dx translator.
Q. Did you require an on-site AE in order to run the translators?
I really wanted to see a seamless translator that anyone could run (comparable to the VB98 migration tool) vs. ton of scripts & manual tasks.
Q. How long did it take you to actually translate and roll out Dx to your teams?
Q. Have you experienced problems since Dx is CES only vs. DC which still allows netclasses/netproperties (stability factor)
Q. What where the gains vs. losses in the migration (symbol wizards, script abilities)
Feel free to share whatever you deem to be reasonable & Thanks
Chris Smith
Application Support Analyst
National Instruments
www.ni.com
I've recently migrated from VeriBest to PADS 9, and I'm missing that "old" pan feature with mouse rigth-click-and-hold, which is similar to the one used in Altium Designer.
By default, pan feature is now configured with mouse middle-click-and-hold, but it has a somewhat different behaviour.
Is it possible to configure DxDesigner with that "old" pan setting?
Thanks.
Hi group. I have a long history with DxDesigner (back to ViewDraw) but not in the past several years, I've detoured through OrCad, CadStar, and KiCad. Starting again with version 9.5 and the ES suite.
If I remember correctly I used to import FPGA output pin/pad files directly into the symbol wizard to create hetero symbols, some work required but the result was good and very flexible. Is this functionality gone now? I see that I can import a CSV file and create a single symbol directly from that, or I can use the symbol wizard to create a fractured symbol and import a Verilog or VHDL file.
1) Is there a way to create a fractured symbol from a CSV file?
2) Or is there a way to create a symbol from a CSV import, and then fracture it later?
3) If I import a Verilog/VHDL file through the symbol wizard is there a way to supply pin numbers too?
I don't mind massaging my CSV source file into any format that will allow me to import the information directly, I just don't want to create 324 pins from scratch with names, numbers, and directions. In this case it's a custom ASIC so no files from ISE/Quartus/etc. or third-party symbols.
If this functionality is (no longer!?) part of the library editor, has anyone created a tcl script or external tool to do this? Seems like it would be of use to a lot of people.
Best.
Hi all,
I am using EE2007.9.4.
I have 4 DDR'S connected to processor in my design.
I need length report with fan-out length of all individual IC's.
Is it possible?
Thanks in advance.
Murali Bala
Maybe someone can help me here. The attached image shows four splices I have in a harness. Splices 7 and 10 the table is placed properly, on splices 13 and 8 the table falls within the bundle. Is there a way to move the table out of the bundle and to the left of the splice and not effect splices 7 and 10.
Thanks,
Jay
Running Dxdesigner, I need to upgrade my computer and move all my projects to a new machine. What is the correct way to do that?
I tried simple copy, do not work, getting the "unable to open icdb connection"
tried migration copy too, do not work.
Tried icdb server to view the server, getting the same error.
Seems it is trying to open a database based on old machine's name? \\oldpc\work\...., but not on the local directory.
When I tried to open the project on a new machine, it still try to access \\oldpc\...
I tried to change the oldpc 's name to something else, I will get the same error. I guess I could change the new machine to the oldpc name, but that would not be elegant.
I noticed the database\icdb.dat contains the machine name and user name. I wonder if that is the parameter I should change? If so, how do I change?
Anyway, what is the right way to copy projects from old machine to a new machine? I never had the problem with design Capture. Were forced to use dxdesigner now .
Hi Guys:
I am building an EE2007.5 DxDesigner/Expedition ECAD system using the icdb interface. In earlier versions of DxD I used the symbol attribute PKG_TYPE to point to the footprint cell. With icdb there seems to be no use for PKG_TYPE so I want to use the Cell Name property attached to the DxD symbols in order to pass the footprint cell to a Bill of Material using the icdbPartsLister.exe software. Packager will not populate the Cell Name property in DxD. icdbPartsLister.exe will not read the Cell Name property in the common database. (So much for the icdb common database?) The correct footprint cell does get passed to Expedition for layout. This is a Packager and icdbPartsLister problem(s).
If I have to use the PKG_TYPE attribute, I must build a resistor symbol for each resistor footprint cell that may be use in a design. (Each part in our library points to only one manufacturer's part number or a specification control drawing. This reduces BOM and PCB footprint errors.) The libraries are built differently for PKG_TYPE vs. Cell Name.
Has anyone got a fix for this?
Thanks,
Dwain
PS: The argument ordering in the help files for icdbPartsLister.exe and icdbPartsListerGUI.exe is not correct. Use icdbPartsLister.exe -d -i -b -o
Hi,
I want to confgure the DxDesigner RDC in a way to solve the following issue:
Find all nets, in our flat (not hirarchical) design that do not have an on/offsheet symbol connected to tehm and are are used on same or other page of the schematic.
Example:
Now it gets more complex:
The last redundant flat symbol check is neither mentioned in the documentation nor I can configure it.
Does anybody know, how to get rid of those messages and only find the connectivity issues?
Kind regards,
Andreas
Is it possible to get the minimal trace to trace information on an existing PCB with automation?
best regards
Wolfgang
I thought I had seen something about this in release notes somewhere, but I can't find it now.
I have multiple GND planes (digital, analog, RF, shield) that all need to be referenced together at a few locations on the board. I've got some tricks, like copper only decals with overlapping pads. But to use these with an IPC netlist test in my CAM editor, I have disconnect them all, run the artworks and checks, then reconnect them to run final artwork. I don't like having to cheat software to get what I need.
Is there some function in PADs to connect two different nets? Does anyone have other ways of doing this?
Pete
I'm just wondering how people like the notification streams in the new communities.
If have a pin property in the Library Signal which shoudl be styled to be visible on the diagram. Since the library properties can not be altered we need to provide a mechanism to allow a user to display an alternate property. A pin property Pin Function was created in the project object type information section. We have both properties listed in the styling. the pin function property has no query, and the signal property has this query for (DevicePin) evaluate (not (value exists (property PIN FUNCTION)))
The issue is this query appears not to be checking if a value exist for Pin Function, but if the property itself exist as if we add the property (auto assign) the signal property will not show.
How do we right a query so that when there is a value for the pin function property the signal property is not visible.
Hi,
I have created a library "abc_common_library" using the following command.
vlib abc_common_library
I have a package file "abc_common_pkg.vhd" which I want to include in the library "abc_common_library". I place the vhdl file in the folder abc_common_library but it shows empty sign. Kindly let me know how to include package or how to compile library with package. The package of this library is used in test bench.
Best regards,
Bilal
I need to DRO, move the via, DRP - and it is okay. But I cannot place via with design rule prevent in place. I checked the pad entry, via at SMD, and it did not fix the problem.
In many case, I need to straighten out a trace with a little kink in it. To do that, I have to manually move the cell by very small amount. And that can be very tedious.
I wonder if there is a faster or automatic way to accomplish that?
thank you,
Hi all, currently using PADS Layout & Logic 9.4.1 and still do not see a solution to this problem/question. This problem/question lies on the manufacturability/ SMD Assembly side of the PCB world. It's not a problem that will show itself in the netlist or electrical correctness of the circuit.
I see in Design Rules, Clearance, in the Clearance Matrix there is a SMD to SMD rule the user can specify. That rule is relevent for different net SMD to SMD clearance rules. But what about same net SMD to SMD clearance? Hmmmm, you ask why would anyone care about that? Well as I hinted above this concern is not explicitly speaking a problem electrically for the circuit to function properly but a manufacturability/SMD assembly problem. If SMD pads of adjacent devices are too close together there will be either no solder mask web between them, or a mask web so thin that solder paste will wick under the mask web anyway, when the web is over Copper. We have seen in our own in house SMD assembly process that any solder mask web less than .004"-.005" will not prevent solder paste migration, again when the web is over Copper.
So, if you have SMD pads of adjacent devices that are that close, or even up to .010" apart (the PCB FAB house is going to grow those solder mask openings to allow for relatively poor solder mask registration leaving the PCB with maybe only a .005" web) and those SMD pads are in a Copper plane/pour they are effectively going to be one SMD pad. Again, not a problem electrically but all kinds of bad things can happen on the SMD assembly line. Components could start to float/drift out of position, tombstoning, a larger component could steal all of the solder from a smaller one, take your pick of problems. Of course AOI will catch these problems but if you are waiting for AOI to catch your problems you've already committed the mistake to a fabricated PCB and signed up for expensive hand solder rework AND another spin of your PCB. Better to catch it up front right?
A new rule in the Design Rules, Clearance, Same Net Matrix for SMD to SMD would catch this type of problem right?
Is there some specific reason Mentor has seen fit to not include this Design Rule?
Is there some aspect to Decal design that I am not familiar with that can effectively prevent this, and/or allow existing design rules to flag this type of problem?
The attached picture shows just such a problem between L4 and (C81 & C82).
Hi,
I've been using PADS 9.5 and Solidworks Premium 2013 for quite a while now and I wanted to share my experience.
POST REVISION:
This is revision B of my post
NOTE:
You need the Premium version of Solidworks because it comes with Circuitworks.
Circuitworks is the piece of software that reads PADS netlist ASCII files and translate them into a Solidworks .SLDPRT file
During Christmas time you might purchase the Premium version of Solidworks at the price of the standard version: 5000 Euros
WORK FLOW:
1. Export the PADS ASCII 2007 netlist (I tried other versions but 2007 it's the one that works perfect)
2. Import the ASCII netlist into Solidworks
3. Wait 10 to 30 seconds for Solidoworks to build the 3D file of the board
4. The 3D file created is an assembly file
NAMES MATCHING:
Solidworks reads the PART TYPE of the component.
The 3D files of your components must have the same name of the PART TYPE of the components in PADS.
3D FILE TYPES OF YOUR COMPONENTS:
Use STEP files for your components. They are light weight.
To find the 3D files of components, just browse in 3DContentcentral.com or directly in the IC manufacturers's website
SOLIDWORKS LIBRARIES:
Solidworks doesn't store the 3D files of your components into a single big library.
You may place the 3D files whereever you want. Just tell Solidworks where they are.
I, for example, store my 3D files a network path.
COMPONENT ROTATION AND SHIFT:
You might need to rotate or shift one or more 3D files in Solidworks
TWO-WAY OPERATIONS:
If you move a component within Solidworks you may export the new netlist and import it back to PADS.
To be honest I've never tried this function.
I've been using one-way operations so far.
PCB THICKNESS:
Set the PCB thickness within PADS.
MULTILAYER PCB:
They are perfectly translated into Solidworks.
3D ELECTROMAGNETIC SIMULATION WITH CST OR ANSYS:
Never tried.
I doubt though it can be done because to save file space, all copper pieces are considered one solid body in Solidworks.
CST PLUG-IN FOR SOLIDWORKS:
CST 2014 reads Solidworks native files.
BOARD CUTOUTS:
They are perfectly translated into Solidworks.
DXF drawing in the PCB file:
They are perfectly translated into Solidworks.
LAN network path:
Solidworks works fine over a LAN.
You can place the 3D files of your components in a network path.
PC CONFIGURATION:
My PC configuration is:
Windows 7 Pro, Intel i7, 8 GByte RAM, 2 Hard disks, 90 dollars Video card (GPU)
Solidworks works perfectly with low cost video cards.
In case of 3D boards with more than 150 components, you might need to check a property in Solidworks: "Large Assembly View Option"
WHY I DIDN'T PURCHASE ALTIUM:
I needed a real 3D CAD software.
Enrico Migliore