Dear Calibre users,
We are receiving a "COMPONENT TYPES WITH NON-IDENTICAL SIGNAL PINS" message during Calibre LVS (attached below) of a Cadence custom flow design using some standard cell abstracts from a vendor. It is suggesting that some of the pins will be ignored for LVS, and in my initial testing, that appears to be the case. I am attaching a contrived example of two back to back inverters whose supplies are shorted in the schematic but are left open in the layout (and LVS does not complain).
Do folks have any thoughts or suggestions on how to deal with this? I can provide a bit more background if it helps:
Basically we are using the LVS BOX command to black-box some standard cells for LVS (we have abstracts/layouts with the metal and pins only, no devices). In the Calibre GUI, under "Include SVRF Commands" we add an LVS BOX command for each cell we use.
The problem appears to be two things:
1) that the vendor schematic subcircuit for the cell has 4 cadence global "inherit" supplies: vdd, vdds, gnd, and gnds, whereas the layout just has two supply pins, "gnd" and "vdd" in the layout (substrate connections happen in filler cells).
2) that the source subcircuit for the cell names the supplies as inh_gnd, inh_gnds, inh_vdd, and inh_vdds after auCdl export (seems to follows auCdl convention that I have seen with other PDKS...), whereas the layout only has "vdd" and "gnd" named terminals.
In the example below, we are mapping the 4 inherited connections in the schematic using the usual cadence method of using netSet properties on the cell, mapping to our own 2 supplies called MY_VDD and MY_GND (vdd and vdds assigned to MY_VDD, gnd and gnds assigned to MY_GND). You can see the example schematic netlist seems to have it right, but the layout netlist does not match. Presumably LVS is not flagging this as a comparison mistake because it already announced it would not compare some of the pins via the NON-IDENTICAL PINS message?
Any insight on the right way to deal with this without a lot of copying and editing of the standard cell pins would be greatly appreciated...
Best,
Phil
-------------------------------------------
MESSAGE:
SC_IVX4 was treated as an LVS Box
**************************************************************************************************************
COMPONENT TYPES WITH NON-IDENTICAL SIGNAL PINS
**************************************************************************************************************
(Cells with the same ( or corresponding ) name that have different signal
pin names are listed below. Pins that do not appear in all corresponding
cells in both source and layout are ignored by the comparison algorithm.)
Layout Component Type: SC_IVX4 (4 pins): gnd vdd a z
No Extra Pins.
Source Component Type: SC_IVX4 (4 pins): a z inh_gnd inh_vdd
Source Extra Pins: inh_gnd inh_vdd
-------------------------------------------
SCHEMATIC NETLIST:
************************************************************************
* auCdl Netlist:
*
* Library Name: sandbox
* Top Cell Name: test_std_cell
* View Name: schematic
* Netlisted on: May 27 17:44:10 2015
************************************************************************
.INCLUDE devices.cdl
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: CORE_SC
* Cell Name: SC_IVX4
* View Name: cmos_sch
************************************************************************
.SUBCKT SC_IVX4 A Z inh_gnd inh_gnds inh_vdd inh_vdds
*.PININFO A:I Z:O inh_gnd:B inh_gnds:B inh_vdd:B inh_vdds:B
MMN1 Z A inh_gnd inh_gnds nfet (//device parameters)
MMP1 Z A inh_vdd inh_vdds pfet (//device parameters)
.ENDS
************************************************************************
* Library Name: sandbox
* Cell Name: test_std_cell
* View Name: schematic
************************************************************************
.SUBCKT test_std_cell IN MY_GND MY_VDD OUT
*.PININFO IN:I OUT:O MY_GND:B MY_VDD:B
XI4 INTERNAL OUT MY_GND MY_GND MY_VDD MY_VDD / SC_IVX4
XI0 IN INTERNAL MY_GND MY_GND MY_VDD MY_VDD / SC_IVX4
.ENDS
-------------------------------------------
LAYOUT netlist:
***************************************
.SUBCKT SC_IVX4 gnd vdd A Z
** N=10 EP=4 IP=0 FDC=0
.ENDS
***************************************
.SUBCKT test_std_cell IN OUT MY_GND MY_VDD
** N=22 EP=4 IP=12 FDC=0
X0 MY_GND MY_VDD IN 5 SC_IVX4 $T=1300 1310 0 0 $X=0 $Y=10
X1 6 9 5 OUT SC_IVX4 $T=17050 1310 0 0 $X=15750 $Y=10
.ENDS
***************************************
