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HCELL selection for LVS

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HCELL selection can be a controversial topic. I would like to describe a few different techniques, the rationale behind those techniques, and hopefully generate some discussion based on your experiences.

 

One technique focuses on performance. In the interest of fastest turnaround time, we can choose cells based strictly on the potential time savings that choosing any particular cell may bring. Any cell containing just a few devices, and then placed just a few times, would offer little value from the standpoint of performance. On the other hand, a cell that contains several thousand devices, and placed multiple times, is a good candidate for the hcell list. Calibre Interactive can help create an hcell list of this nature. From the command line, it can be invoked with "calibre -gui -lvs". Several fields will need to be filled in for netlist names, top cell names etc. The process is described in the "Calibre Interactive User's Manual" in the section titled "Performing Hcell Analysis in LVS". A high performance hcell list may have a surprisingly small number of hcells... Possibly less than 10 or 20 cell names. While the performance aspect of this method seems clear enough, I do sometimes wonder if the small number of hcells ever has a negative side effect of increased difficulty for LVS debug.

 

Another technique focuses on "design methodology" instead of performance. Some people use hcells as a means of enforcing a design methodology where hundreds or thousands of cells with the same name in the layout and source are expected to match at the cell level. The "-automatch" switch, or an exhaustive hcell list of practically all the layout and source cells may be used for this method. It's not necessarily best for performance, and can lead to nuisance errors in many cases, but many people use this method. I would be interested to hear your opinions related to this method.

 

A third technique begins with listing all the standard cells, and adding certain other cells based on some criteria. I presume that familiarity with the design is necessary for this method. I haven't used this method myself so I'm a little vague on the details. If you have had good or bad experiences with this third method, please share.

 

I have often wondered if Calibre could offer a simple and automatic hcell selection option that gives optimum performance, avoids false errors and promotes easy debug. Maybe our collective discussions will lead to the answer.

 

 

 

I will collect and summarize replies for this thread into a document we can refer to. Here's a link to that document: HCELL selection methods


I use multiple size vias in design. How can I change their size to single size? Is there any selection filter to select and change via sizes?

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I use multiple size vias in design. How can I change their size to single size? Is there any selection filter to select and change via sizes?

Rename Layers via CES Stackup - Editor

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Hey Guys,

 

I would like to add and rename some of my layers.

Since today, I hadnt any problems with it so I just went to the CES steckup editor and added 2 new layers to my stackup.

so far so good, for sure the new names dosnt match to my stackup and so i tryed to rename the layers (SIGNAL_4 -> SIGNAL_5) but i wasnt alowed to rename the last layer. (the midlayers worked well)

on the right side (where i can see the stackup picture) a red massage came up: "Metal layers cannot be added before the first metal layer or after the last metal layer"

maybe someone know this issue and could help me out.

 

thanks and have a nice day (:

 

stackup.jpg

 

 

Is Mentor ready for Windows 10?

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Microsoft announced Windows 10 definitely in the summer, but possibly late July 2015.

Windows 7 and 8.1 PCs will get direct upgrade to Windows 10.

Are all Mentor tools at that time ready for Windows 10?

What is Mentors road path to Windows 10?

PADS VX.1 with PartQuest

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All,

 

PADS VX.1 is now released, with beta support for PartQuest - our web portal with integration into Digi-Key's catalog of components with over 4 million parts!

 

PartQuest allows engineers to search, research, and purchase parts for your designs.  Many of these parts are populated with schematic symbols, footprints, and parametric data, which can be downloaded directly to your xDX Designer and PADS libraries, accelerating design starts.

 

PartQuest has been used with Designer Schematic and Layout since last November. With PADS VX.1 we have introduced integration with PADS net list projects with or without xDX DataBook.

 

 

Checkout the website at http://partquest.com.  There is a video on the homepage that gives an overview, and additional videos to help you get started using the site on the PartQuest Community at https://communities.mentor.com/community/pcb/pads

 

Be sure to post your feedback and comments back here on this forum!

 

Jim

differential trace impedance calculation

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Hello!

 

I am confused about the correct PCB stack-up for 100 Ohm differential trace impedance.

Can you describe me the basic rules for this and advise relevant links?

 

For example, I have differential stripline signals, which should be 100 Ohm impedance.

Dielectric thickness may vary, but at the moment I have 4mils.

Trace thickness is 0.6mils.

 

So I need to choose the correct trace width/spacing, am I right?

Previously I was used 5mils width and 6mils spacing differential traces.

But when I put all these values to some calculator it gives me only 72 Ohm of differential impedance.

What could be wrong and what should I change in my values in order to have about 100 Ohm impedance?

 

Should I trust to such kind of calculators?

 

Thank you in advance!

 

Veronika

Is there a way to export selected items in PADS layout

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I am looking for a way to export to a text file or excel file, selected items in PADS layout.  I would like to select several nets on my layout and be able to export those to a text file or excel file.  Thank you for any help.

Image to Layout (Logic)

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I was trying to use the good old bmp2asc program to import a bitmap into Layout.

But I couln't figure out a way to make it working under Win 7 x64.

So I gave up bmp2asc and I wrote my own script which can be run from within Layout and it also presents a GUI.

The file is attached to this message. Please post your questions here in case you have problems.

Enjoy!

BR


Importing a .sch Schematic

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I am trying to import the attached schematic file into PADS. Has anyone been successful in do this?

 

The file represents TI's MSP-EXP430F5529. The file can be downloaded here also:

 

MSP430F5529 USB LaunchPad Evaluation Kit - MSP-EXP430F5529LP - TI Tool Folder

 

We have imported the schematic into Designer Schematic but not in PADS. Aren't Designer Schematic and PADS developed by the Mentor Graphics?

 

Your help would be much appreciated.

Getting "hyperlinks" into the DxDesigner Output Window

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I have a utility that scans a schematic extracting Bill of Material information. As part of the extraction process component attributes are checked against our internal company standards. If any components are found to be in error (e.g Value set to TBA!, part numbers not specified etc) then details are listed to the Output Window in a new tab. So far so good.

 

What I really want now is to be able to click on a line on the output window and then have the the system select and zoom in on the corresponding component. Now either there is some special format I have to use when writing to this window or I have to make use of the IHtmlCtrl->RegisterErrorExpression function (exported from OutputWindow70.dll). Either way I am now stumped by the total lack of documentation / example code. Has anyone else come up against this?

Why must nets be assigned to a split/mixed plane layer?

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I'm wondering what is the reasoning to have to assign nets to a split/mixed plane layer.  Why can't any net appear on a split/mixed plane layer?

 

We have made it a custom to flood component layers with copper (ground) using copper pours.  But copper pours have a lot of limitations.

 

Am I going to run into problems if I set a component layer to split/mixed plane, and then assign all nets to that layer?

pads.com website can't download software

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Pads.com site can not download the evaluation version of the software is always stay in a page, there is no place to suggest to the login account

无标题.jpg

Few Questions in Xpedition Vx

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HI Experts,

 

Could you help me to xplore few options in Vx?

 

1. How to extract component and trace properties? In EE7.9.X, we used Report writer to explore many physical and electrical properties. In Vx, I ran report writer but it just says "Report writer data was successfully generated"

 

     - Any license required to launch complete version of report writer.

 

2. How to extract IPC-D-356? I can export "IPC-D-356B" from File -> Export but I need IPC-D-356 as like EE7.9.X. It seems ipc356.exe removed from VX

 

-Arunraj

Solder Paste Layer 면적 계산

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Solder Paste Layer 면적을 계산하기 위해 아래와 같이 하였습니다.

Solder Paste Layer에 User가 Draw한 object는 계산 되지만, Library에 포함되어 있는 Solder Paste는 계산이 안됩니다.

Library에 포함되어 있는 Solder Paste 면적을 계산 하기 위해서는 어떻게 해야 하나요?

 

Dim mskeng
    Set mskeng = CreateObject("MGCPCBEngines.MaskEngine")
    Scripting.AddTypeLibrary ("MGCPCBEngines.MaskEngine")
    Scripting.AddTypeLibrary ("MGCPCB.ExpeditionPCBApplication")


Dim stenColl

    Set stenColl = pcbDoc.FabricationLayerGfxs(epcbFabSolderpaste, epcbSelectAll, epcbSideTop)

 

Dim stenUs, shapesCu

    Set stenUs = mskeng.Masks.Add
    Set shapesCu = stenUs.shapes

Dim stenobj, pnts

    For Each stenobj In stenColl
  pnts = stenobj.Geometry.PointsArray
  Call shapesCu.AddByPointsArray (1 + UBound(pnts, 2), pnts)
Next

Unlock Reuse Block in xPCB

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We recently moved from Expedition to Xpedition. In the layout we have reuse blocks. Now we want to move a reuse block, but it complains about "Can not modify locked objects"

How to unlock the reuse block. The icons remain disabled. Also through the properties we cannot reach the lock state.


Need to create my own RPL file in the report writer

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Hi All,

 

We are creating cells with user defined properties. In default cellpartition.rpl  file has not generating the custom properties. How to edit or create the new rpl file.

 

 

Regards,

AnG..

sub net error in PADS Layout ?

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Hi everyone,

I am facing some error while generating connectivity report.even that net connected but getting error only.

 

 

 

 

CONTINUITY ERRORS REPORT -- PRJA2133_PCB03_20150423_8.pcb -- Thu Apr 23 21:08:45 2015

Isolated subnets for: CS12-

*** subnet # 1

J2.6

*** subnet # 2

DRILL(J2.6 L1) HATCH OUTLINE(7944.1,6430.38 L1) HATCH OUTLINE(6064.1,6867.3 L1) HATCH OUTLINE(4634.1,8877.3 L1) HATCH OUTLINE(7944.1,6430.38 L2) HATCH OUTLINE(6064.1,6867.3 L2) HATCH OUTLINE(4414.5,8317.3 L2) D3.2 R48.2 U27.1 R29.1 R28.1 R27.1 R26.1 R25.1 R245.2 R41.2 R47.1 C4.2 U1.2 C35.2 Q64.2 R431.2 R456.1 R455.1 Q6.2 Q6.4 Q11.4 Q11.2 VIA(4390,8715.49 L1) VIA(5683,7668.49 L1) VIA(5750,7390.49 L1) VIA(5694,7569.49 L1) VIA(6045,6980.49 L1) VIA(6040,7145.49 L1) VIA(6385.74,6948.49 L1) VIA(7350,7155.49 L1) VIA(6291.63,7569.49 L1) VIA(7060,6445.49 L1) VIA(7165,6450.49 L1) VIA(7425,6450.49 L1) VIA(7295,6450.49 L1) VIA(7930,6450.49 L1) VIA(7685,6450.49 L1) VIA(7555,6450.49 L1) VIA(7815,6450.49 L1) VIA(5605,7070.49 L1) VIA(6045,7225.49 L1) VIA(5680,7400.49 L1) VIA(5605,7150.49 L1) VIA(5680,7235.49 L1) VIA(5680,7315.49 L1) VIA(5755,7060.49 L1) VIA(5750,7225.49 L1) VIA(5895,7225.49 L1) VIA(5685,7070.49 L1) VIA(5820,7390.49 L1) VIA(5895,7305.49 L1) VIA(5980,7225.49 L1) VIA(5685,6895.49 L1) VIA(5825,6885.49 L1)

 

Isolated subnets for: CS10-

 

 

*** subnet # 1

J2.19

 

 

*** subnet # 2

HATCH OUTLINE(10264.1,6430.38 L1) HATCH OUTLINE(8338.7,6867.3 L1) HATCH OUTLINE(6804.1,6867.3 L1) DRILL(J2.19 L2) HATCH OUTLINE(10264.1,6430.38 L2) HATCH OUTLINE(8338.7,6867.3 L2) HATCH OUTLINE(6804.1,6867.3 L2) U33.1 R276.2 C10.2 VIA(8040,7355.49 L1) D16.2 R17.2 R110.2 VIA(6510,7265.49 L1) R16.1 U11.2 C36.2 Q68.2 R429.2 Q24.2 Q24.4 Q5.2 Q5.4 R8.1 R9.1 R7.1 R6.1 R5.1 R453.1 R454.1 VIA(8561.63,7567.4 L1) VIA(8200,7550 L1) VIA(8175,7355.49 L1) VIA(9611.5,7101.99 L1) VIA(8705.74,6945.49 L1) VIA(8325,7265.49 L1) VIA(8325,7190.49 L1) VIA(8040,7265.49 L1) VIA(8325,7355.49 L1) VIA(8105,7355.49 L1) VIA(8255,7265.49 L1) VIA(8070,7145.49 L1) VIA(8175,7190.49 L1) VIA(8105,7190.49 L1) VIA(8255,7190.49 L1) VIA(8070,7040.49 L1) VIA(8075,6945.49 L1) VIA(8045,6900.49 L1) VIA(8140,6890.49 L1) VIA(8290,6890.49 L1) VIA(8175,7265.49 L1) VIA(8040,7190.49 L1) VIA(8105,7265.49 L1) VIA(8255,7355.49 L1) VIA(6775,6895.49 L1) VIA(6730,7265.49 L1) VIA(6655,7265.49 L1) VIA(6545,6890.49 L1) VIA(6775,7055.49 L1) VIA(6775,6975.49 L1)

Isolated subnets for: CS9-

Planned Release Date for PADS flow VX.1

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Does anyone have a good idea of when PADS Flow VX.1 will be released?  Trying to decide if I should have the IT group install VX.0 in over 20 users computers or wait a few weeks for VX.1.  The BSD Release Information by Product (September 2014) showed VX.1 for Pads November 2014.  http://supportnet.mentor.com/news/bsd_planned_releases.cfm

Charging Circuits and Ring Terminals

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Good afternoon everyone.

 

I need to advice/direction with regards to ring terminals.

 

In one of the harness designs that I am working in we have multiple alternators.  Some of these alternators have an option of having 1Ga or 2Ga cables (customer's choice).  On the starter end of the power cable, we use fuse links.

For every 2Ga power circuit we use 2 fuse links that terminate in a single ring terminal.

For every 1Ga power circuit we use 3 fuse links.  Two links terminate in one ring terminal, and one link in another ring terminal.

 

I'm kind of stumped on how this should be set-up in the Integrator plane.  We are using the generative process.

 

I am wondering if this will just have to be added manually after synthesis is ran.

 

 

Thanks!

Questions and Answers from June 2 Webinar "PADS 9.0 Flow Overview"

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Dear all -

 

This thread will serve as a question and answer forum from the June 2 "PADS 9.0 Flow Overview".Please use this thread to start discussions or seek further interactions on topics of interest to you.

 

For those of you who did not get to view this webinar - please go www.mentor.com/pads there you will be able to view the following on-demand content:

 

  • PADS 9.0 Flow Overview Webinar (an overview of the flow and the components that make up PADS 9.0)
  • What's New in PADS 9.0 Webinar (a deeper look at what is new in this release)
  • On-demand demonstrations
  • PADS customers speak out about PADS

 

Let's use this community to interact with each other - our goal is to create a truly global interactive platform for all things PADS.

 

Let us also know if you have suggestions for improvement.

 

Thanks.

 

Ed.

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