Hello,
I used in EE7.9.5 a script for generating the Variant Schematics PDFs and Partlists.
I changed now as described in the EEVM Automation section to "MGCVARIANTGUI.MGCVariantGUICtrl.2"
But the following code does not work - since following error comes up:
Variable not defined => eVMOperNone.
For each vmCompMod in VmDocObj.ComponentModifications(var.Name)
if vmCompMod.Operation = eVMOperNone then
end if
next
The same code works in EE7.9.5 - whats wrong?
Wolfgang
What are the differences between global nets and regular nets? It seems that I can use them interchangeably. I understand that I should use the global nets for power and ground only (in general), but this does not really tell me the difference.
Hello
(Currently using Expedition 7.9.1, but also access to Expedition VX).
Is it possible to export symbols and cells from our Expedition library into a format that can be read by other ECAD tools.
I can export the parts to HKP files, but is there then a translator available to convert to other formats as no other tool seems to be able to read hkp files.
I was trying to use the good old bmp2asc program to import a bitmap into Layout.
But I couln't figure out a way to make it working under Win 7 x64.
So I gave up bmp2asc and I wrote my own script which can be run from within Layout and it also presents a GUI.
The file is attached to this message. Please post your questions here in case you have problems.
Enjoy!
BR
Hello all,
can you please help me to choose the graphics card to my new notebook... not to have a problems with performance, driver..... (or minimum)(best supported)?
1) I can choose the NTB with integrated graphics card on chip (HD4600.....on Intel Core i7-4810MQ) AND AMD FirePro M6100M w/2GB GDDR5
or
2) either integrated HD4600 OR.... AMD Radeon HD 8790M 2G GDDR5
or
3) without integrated graphics card .... NVIDIA Quadro K1100M w/2GB GDDR5 or NVIDIA Quadro K2100M w/2GB GDDR5 or AMD FirePro M5100 w/2GB GDDR5
I would prefer NTB with the option 1 but I'd like to know some experience , known issues, troubles... to better decide.
Can somebody recommend me the the best solution?
Many thanks
Martin
I bought a license for our new build server (VM running Win7 Ultimate on VMWare Workstation 10.0.4) and installed it via the
Sourcery CodeBench IDE (Version: 2014.05-36). The IDE accepted the license but when running the ARM compiler, following
error occurs (see error.txt):
No such feature exists.
Feature: gcc_ARM_EABI
The license path is correct and the host id is correctly detected too. The license contains following entries
INCREMENT armsptarmeabi mgcld 2016.030 3-sep-2015 0 7ED65672676DD8C05ECA \
VENDOR_STRING=56B123DF HOSTID=000c297ed211 SN=48048790 SIGN2="194A \
8BAB 7955 C18F 69F7 10F6 D6C4 E57E 5A86 6923 E199 0E86 C60A 9AE5 E085 \
0138 1DBD F2DE 202B B0A1 D44C FA43 D84E 1216 30AE D853 4C51 0BC6 3354 \
D529"
INCREMENT gccarmeabi mgcld 2016.030 3-sep-2015 0 0ED6C6D2D8916DCC435F \
VENDOR_STRING=504278E8 HOSTID=000c297ed211 SN=48048789 SIGN2="161A \
2DB2 0301 EDE6 F2AB 1A97 B866 7479 1DD7 536A 4C58 C9A7 814B 31D0 B11B \
070E 95BE 4136 A8CD 3E0E 2EFF CC78 6C74 0A7D AE72 3592 BFBF F7BE DEEF \
DD1B"
INCREMENT idearmeabi mgcld 2016.030 3-sep-2015 0 3E66B6D2A38BD662ABCA \
VENDOR_STRING=51524892 HOSTID=000c297ed211 SN=48048788 SIGN2="0C67 \
FE19 1909 7B43 7250 9D00 C749 AAE2 21BF 4C39 CC76 330D CDE4 881F C7DA \
07E4 6138 61D5 8995 57C1 62E0 815A E1A6 6AA6 1B73 24E4 ED76 93F2 7CF3 \
BBA2"
INCREMENT scbmultilibs mgcld 2016.030 3-sep-2015 0 6E0626424DAA51A75D30 \
VENDOR_STRING=0630CFBA HOSTID=000c297ed211 SN=48048791 SIGN2="07E3 \
3089 2695 2A09 5A7F 5B0B 70CD 76E0 AE46 EFB2 8029 EA15 96AD 1082 E3CE \
07F0 9293 1A60 B19E DDB4 FE13 C489 451D 7A82 778A 1052 F4B7 45D9 760D \
EE6B"
Why am I getting this error message?
Any help or hint much appreciated, I've been struggling 3 weeks on this and Mentor's support
couldn't help so far.
Yann
Can anyone tell me if there is a way to flip a completed design in Expedition without losing any routing. Thanks.
I'm working with the v1.0.0 realease of the ATSAM3UEK bsp but I don't think code is being downloaded to the board during debug.
I'm using a Jlink to debug the Kernel Demo as a Nucleus application. The project appears to build without issue.
It seems that the Jlink connects to the board and Codebench will seem to step though the code - moves to next source line in csgnu_asm.S on each Step Over (Jlink activity light blinks on each step). However, in the Disassembly window, *all* instructions are listed as "movs r0,r0".
If I click on gdb in the Debug tab, it lists the following messages:
warning: while parsing target description (at line 38): Register "CR" has unknown type "CR"
warning: Could not load XML target description; ignoring
warning: while parsing target description (at line 38): Register "CR" has unknown type "CR"
warning: Could not load XML target description; ignoring
Is there some initial configuration that needs to be done to use the Jlink? The release notes indicate that the bsp is compatible with the Jlink.
Regards,
Galen
Hi Experts,
Is there any way to extract customized netlist from dxdesigner schematics?
In design capture, I used "CAE Extractor" from "Report Writer" and directed it to the project .prj files then-extracted various reports, But I cant use it for DX Designer.
Whenever I use report writer, Its ends up with various errors. Repeated error is "database.esf" not found!
Any help?
-Arunraj
Hellow
I am new to PADS in expedition we can export layer by layer length report, is it possible to generate layer by layer length report for PADS layout?
If possible plese provide information to get layer by layer length
regards
AGXIN.J
Hi everyone!
I am new and trying to learn to use PADS(DxDesigner).
I somehow managed to figure out how to create schematic, how to create libraries and how to route PCB(all steps seperately, not together as I will explain).
I am having problems with annotating the schematic.
For a starter, I put few resistors(copied form Optimum Design Libraries), few capacitors(same as resistors) and few ICs(my design) into schematic.
Resistors have reference designators "R?", capacitors "C?" and ICs "U?".
But when I run the packager, it replaces all Ref Designators with Un (n is a sequence number of the element, basically, all Rs and Cs are replaced with Us)!
Somehow, I could not find the settings to correct this!
Also, I am wondering, why can't I replace existing reference designator (for example: U2) with default "U?". The question mark is reported as being invalid option.
But when designing a library, it is perfectly valid to use "U?" for reference designator.
Why so?
Am I missing something?
regards, Jernej
When I generate a netlist in DxDesigner, it generates the beginning of the .asc file with the format:
REFDES DEVICE@PKG_TYPE
for each of the components in the schematic. I'm interested in modifying the .cfg file so that I can use my own property instead of DEVICE. How would this be done?
In the LVS report, I found there were missing instances layout. After checking the source netlist, I found those missing instances were empty subckt in my cdl netlist. Meanwhile, layout cells with same cell name were found in layout but not in layout netlist. There was no devices in that layout. (metal, poly, nw, with pins on some of the wires./not all the wires) Those cells seemed got flattened into top level that caused the mismatch. I used "preserved cell", but not working. Only way to make it work right now is black box those cells. I have concern of using black box. Is there any another solution for that issue?
Thanks,
Qing
I have a split plane gap with 2 Plane Areas that have different Net Names (i.e. +24V and +3.3V). I want to maintain a 30 mil gap between these two floods. What is the best way to accomplish this?
Hi, I would like to write a script to extract all parts of schematic (RefDes, Part Name, etc.) and also the Nets connected to this part? Any pointers on how to do this?
I have read the threads in this space and it is very difficult to find tutorials and help. Links that are hosted by mentor graphics seem to be depricated (page not found and such). The examples in the help of DxDatabook are not helping me with what I'm looking to achieve.
Finally, I downloaded AATK sources, but couldn't find what I need in there. Maybe I missed something because I am looking at the scripts with Notepad++ because I failed to find a way to edit scripts using DxDesigner. Open only seems to let you run an efm, not edit it.
Thanks in advance for helping me!
Hello All.
On WindowsXP, when I need to display a file selecting dialog, I use the following object: Set objDialog = CreateObject("UserAccounts.CommonDialog").
On Windows7, this doesn't work.
I would like to hear from Windows7 users: what object do they use when they need to display a file selecting dialog?
Oleg
I need a way to narrow down the number of matches when I perform a 'replace' in the variant manager. I cannot use the part name as a match condition since there are parts with different part names that needs to be exchangeable, e.g. 'RM0603' needs to be replaceable with 'P0603' (both are SMD resistors with 0603 shape but different tolerances etc.) so for now the library partition is set up as match condition meaning if I want to replace a resistor I get thousands of matches. This is rendering the repalce function more or less useless at the moment.
My Idea to solve this is to match on the cell name as well. If two parts are replaceable on a PCB they will use the same cell in most cases. Does this mean that I will have to incorporate the cell information as a property in DxDatabook in order to be able to use it as a match condition in VM?
Does this property have to be separated from the property 'cell name' that is added when I place a part from DxDatabook and choose another cell than the default one (I guess 'cell name' is the property that is updated if cell info is annotated from Expedition PCB as well)?
If so, how do you suggest I get the data from the central library into DxDatabook? I'm guessing I will have to export the data from the central library into our part database and then load it from their into DxDatabook, but I'm not sure how I would export the cell info.
Pleas feel free to suggest other approaches to narrowing down the number of matches as well. Ideally I would like to match on the part name, but beeing able to change the part name like when you load a component into DxDatabook and replace one of the conditions to match another part.
I'm running the EE7.9.5 flow.
/Björn
HCELL selection can be a controversial topic. I would like to describe a few different techniques, the rationale behind those techniques, and hopefully generate some discussion based on your experiences.
One technique focuses on performance. In the interest of fastest turnaround time, we can choose cells based strictly on the potential time savings that choosing any particular cell may bring. Any cell containing just a few devices, and then placed just a few times, would offer little value from the standpoint of performance. On the other hand, a cell that contains several thousand devices, and placed multiple times, is a good candidate for the hcell list. Calibre Interactive can help create an hcell list of this nature. From the command line, it can be invoked with "calibre -gui -lvs". Several fields will need to be filled in for netlist names, top cell names etc. The process is described in the "Calibre Interactive User's Manual" in the section titled "Performing Hcell Analysis in LVS". A high performance hcell list may have a surprisingly small number of hcells... Possibly less than 10 or 20 cell names. While the performance aspect of this method seems clear enough, I do sometimes wonder if the small number of hcells ever has a negative side effect of increased difficulty for LVS debug.
Another technique focuses on "design methodology" instead of performance. Some people use hcells as a means of enforcing a design methodology where hundreds or thousands of cells with the same name in the layout and source are expected to match at the cell level. The "-automatch" switch, or an exhaustive hcell list of practically all the layout and source cells may be used for this method. It's not necessarily best for performance, and can lead to nuisance errors in many cases, but many people use this method. I would be interested to hear your opinions related to this method.
A third technique begins with listing all the standard cells, and adding certain other cells based on some criteria. I presume that familiarity with the design is necessary for this method. I haven't used this method myself so I'm a little vague on the details. If you have had good or bad experiences with this third method, please share.
I have often wondered if Calibre could offer a simple and automatic hcell selection option that gives optimum performance, avoids false errors and promotes easy debug. Maybe our collective discussions will lead to the answer.
I will collect and summarize replies for this thread into a document we can refer to. Here's a link to that document: HCELL selection methods
Running PADS VX.0 on Windows 7 64 bit machine.
When editing a symbol in symbol editor, I set all colors to "Automatic". I assume that when a user accesses the central library, the component will pick up that user's color scheme.
However, I have found that saving the symbol colors (graphics, pin & text) to "Automatic" seems to always revert back to Black. If I make the colors specific (i.e. pin color =red), that color will persist no matter what the color scheme in xDX Designer is. If I change it back to "Automatic", it reverts to Black regardless of what the color scheme defines.
What's going on? This is very frustrating as I have two CAD guys who have completely different color schemes and I want the symbols to auto adjust to their setup.
Any ideas? Is there a file I can manually edit?
Thanks,
LarryG
It is tough to plow traces for Intel chips (SANDYBRIDGE) , it need layout tool to support arc snake plow. How to do arc snake in Expeditionpcb?. Currently, Cadence Allegro have a special command(16.3 from 2010.8) to support this type of plow, it seems that Cadence have a hard-code special plow to this type of plow. the arc snake plow see the attached picture
Yanfeng