Local symbol usage
I have a design where the blocks to represent one large fpga have been built inside the design as local symbols. I am now ready to build the Part and associate the block symbols into one cell....
View ArticleVesys 2 - Schematic/Harness Ground connections
Hi. I have a schematic with a ground symbol ('device') connected to a 'splice' and wiring from the splice. This looks great on the schematic but gives a problem with Harness:Problem is I have set up...
View ArticleCan we run Expedition PCB Browser on Windows 8.1?
Hello, I use Expedition 7.9.4 on Windows 7 but my customer only have a laptop on Windows 8.1. Do you if he can run the PCB Viewer? It do install. But noting append on launch... :-( Any help?
View ArticleTransitioning from DC(Design Capture) to Dx Designer?
I would like to open a discussion regarding transitioning from DC to Dx Designer for schematic capture: At National Instruments we have been using Design Capture since the days of when it used to be...
View Article"Old" VeriBest pan & zoom (with mouse right-click-and-hold)
I've recently migrated from VeriBest to PADS 9, and I'm missing that "old" pan feature with mouse rigth-click-and-hold, which is similar to the one used in Altium Designer. By default, pan feature is...
View ArticleCreate fractured symbols from a source file?
Hi group. I have a long history with DxDesigner (back to ViewDraw) but not in the past several years, I've detoured through OrCad, CadStar, and KiCad. Starting again with version 9.5 and the ES...
View ArticleLength report with Components fan out length?
Hi all,I am using EE2007.9.4.I have 4 DDR'S connected to processor in my design.I need length report with fan-out length of all individual IC's. Is it possible? Thanks in advance.Murali Bala
View ArticleSplice Table Styling
Maybe someone can help me here. The attached image shows four splices I have in a harness. Splices 7 and 10 the table is placed properly, on splices 13 and 8 the table falls within the bundle. Is there...
View ArticleMove dxdesigner projects to another computer, "unable to open iCDB connection"
Running Dxdesigner, I need to upgrade my computer and move all my projects to a new machine. What is the correct way to do that?I tried simple copy, do not work, getting the "unable to open icdb...
View ArticleEE2007.5 DxDesigner's Packager and icdbPartsLister will not read the Cell...
Hi Guys: I am building an EE2007.5 DxDesigner/Expedition ECAD system using the icdb interface. In earlier versions of DxD I used the symbol attribute PKG_TYPE to point to the footprint cell. With icdb...
View ArticleConfiguring DxDesigner DRC (drc-121 Net Connectivity Consistency)
Hi, I want to confgure the DxDesigner RDC in a way to solve the following issue: Find all nets, in our flat (not hirarchical) design that do not have an on/offsheet symbol connected to tehm and are are...
View ArticleHow to get minimal trace to trace distance on a PCB per automation
Is it possible to get the minimal trace to trace information on an existing PCB with automation? best regards Wolfgang
View ArticleConnecting different GND planes together?
I thought I had seen something about this in release notes somewhere, but I can't find it now. I have multiple GND planes (digital, analog, RF, shield) that all need to be referenced together at a few...
View ArticleHow do you like the notification streams?
I'm just wondering how people like the notification streams in the new communities.
View ArticleQuery to flip property visibility
If have a pin property in the Library Signal which shoudl be styled to be visible on the diagram. Since the library properties can not be altered we need to provide a mechanism to allow a user to...
View ArticleAdding package in common library in QuestaSim
Hi, I have created a library "abc_common_library" using the following command. vlib abc_common_library I have a package file "abc_common_pkg.vhd" which I want to include in the library...
View ArticleHow to configure rules to allow a via in pad during routing?
I need to DRO, move the via, DRP - and it is okay. But I cannot place via with design rule prevent in place. I checked the pad entry, via at SMD, and it did not fix the problem.
View Articleexpedition: How to automatically straighten a trace by fine tune the position...
In many case, I need to straighten out a trace with a little kink in it. To do that, I have to manually move the cell by very small amount. And that can be very tedious. I wonder if there is a faster...
View ArticleNo Design Rule for Same Net, SMD to SMD Clearance
Hi all, currently using PADS Layout & Logic 9.4.1 and still do not see a solution to this problem/question. This problem/question lies on the manufacturability/ SMD Assembly side of the PCB world....
View ArticlePADS 9.5 + Solidworks 2013 Premium - My experience
Hi, I've been using PADS 9.5 and Solidworks Premium 2013 for quite a while now and I wanted to share my experience. POST REVISION:This is revision B of my post NOTE:You need the Premium version of...
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